In general, a buffer memory is provided between two communication systems with different data transfer rates to control a data transfer rate. For instance, the buffer memory is used for the case where a rate at which a transfer source writes data to a buffer memory is higher than a rate at which a transfer destination reads data therefrom.
FIG. 8 is a block diagram showing a construction of a prior art buffer memory control device which temporarily stores data in a buffer memory, and then performs data transfer. Referring now to FIG. 8, a buffer memory (8 bit data input/output, 8 bit read/write address input, read/write enable input) 1 has a capacity of three cells (one cell=53 bytes, 1 byte=8 bits). A write address generation circuit 2 is used for generating a write address of the buffer memory 1. A write address 3 is generated by the write address generation circuit 2. Write data 4 is written to the buffer memory 1. A write enable signal 5 is used for making the buffer memory 1 writable. A read address generation circuit 6 is used for generating a read address of the buffer memory 1. A read address 7 is generated by the read address generation circuit 6. Read data 8 is read from the buffer memory 1. A read enable signal 9 is used for making the buffer memory 1 readable. An address comparison circuit 149 is used for comparing the write address 3 to the read address 7. Specifically, the comparison circuit 149 uses two adders to take the complement of 2, thereby performing subtraction. The comparison circuit 149 subtracts the read address 7 from the write address 3, thereby obtaining a subtraction result 150. An overflow occurrence notification circuit 151 is used for detecting occurrence of overflow in the buffer memory 1 when the subtraction result 150 changes "-1" into "0". An empty occurrence notification circuit 152 is used for detecting occurrence empty in the buffer memory 1 when the result 150 changes "+1" into "0".
FIG. 10(a), 10(b), and 10(c) show constructions of the address comparison circuit 149, the overflow occurrence notification circuit 151, and the empty occurrence notification circuit 152 in FIG. 8, respectively. Shown in FIG. 10(a) are exclusive-OR circuits EX.sub.01 EX.sub.02, EX.sub.11, EX.sub.12, . . . , EX.sub.n1, and EX.sub.n2, AND circuits AD.sub.01, AD.sub.02, AD.sub.11, AD.sub.12, . . . , AD.sub.n1, OR circuits OR.sub.01, OR.sub.11, . . . , OR.sub.n1, bits A.sub.0, A.sub.1, . . . , A.sub.n forming a write address, bits B.sub.0, B.sub.1, . . . , B.sub.n forming a read address, bits S.sub.0, S.sub.1, . . . , S.sub.n of a subtraction result, and bits C.sub.0, C.sub.1, . . . , C.sub.n of a carry.
Shown in FIG. 10(b) are a decoder 51a for decoding a subtraction result "0" of the address comparison circuit 149, a decoder 51b for decoding a subtraction result "-1", a flag register 51c set when the decoder 51b has detected "-1", and an AND circuit 51d for notifying a transfer source of occurrence of overflow when outputs of the decoder 51a and the flag register 51c are respectively high (H).
Shown in FIG. 10(c) are a decoder 52a for decoding a subtraction result "0" of the address comparison circuit 149, a decoder 52b for decoding a subtraction result "+1", a flag register 52c set when the decoder 52b has detected "+1", and an AND circuit 52d for notifying occurrence of overflow when outputs of the decoder 52a and the flag register 52c are respectively high (H).
Hereinafter, operation of the buffer memory control device 1 so constructed will be described. Referring to FIG. 8 again, the buffer memory 1, when the write enable signal 5 is at low level (hereinafter referred to as L level), writes the write data 4 onto the write address 3 output from the write address generation circuit 2 in synchronization with a write clock (not shown). The write address generation circuit 2 sequentially outputs addresses 0.about.158 starting with 0 in synchronization with the write clock when the write enable signal 5 is at L level.
The buffer memory 1, wherein the read enable signal 9 is at L level, reads the read data 8 from the read address 7 output from the read address generation circuit 6 in synchronization with a read clock (not shown). The read address generation circuit 6 sequentially outputs addresses 0.about.158 starting with 0 in synchronization with the read clock when the read enable signal 9 is at L level.
In order to detect occurrence of overflow in the buffer memory 1, the address comparison circuit 149 subtracts the read address 7 from the write address 3, and outputs the subtraction result 150 to the overflow occurrence notification circuit 151 and the empty occurrence notification circuit 152. The subtraction result takes a positive value in normal operation, since a value of a write address is larger than that of a read address. However, if overflow occurs, as shown in FIG. 9(a), a write address WAD passes through a read address RAD, reaches the highest address in a memory area, and then goes back to the lowest address therein, from which it is increased toward the read address RAD. Therefore, the overflow occurrence notification circuit 151 detects overflow when the subtraction result 150 changes from "-1" to "0". On the other hand, if empty occurs, as shown in FIG. 9(b), the read address RAD catches up with the write address WAD, and therefore the empty generation notification circuit 152 detects empty when the result 150 changes from "+1" to "0", and then makes reading stop.
In the prior art buffer memory control device, there have been shortcomings with its use, which will be described below. In a case where cell unit data, i.e., a data set consisting of plural pieces of data, is being written onto a buffer memory, and transfer of the data is aborted prematurely, in order to read the written data therefrom, pseudo data is inserted into the cell as the following data, thereby performing data transfer. In a receiving end, however, the cell unit including the pseudo data is abandoned. Consequently, loss of transmitted data occurs.
As mentioned previously, overflow or empty is detected by the address comparison circuit 149 in FIG. 10(a). The address comparison circuit 149 includes a subtraction circuit which subtracts a read address B from a write address A by performing "A+(two's complement of B)+1", so that an increase in the number of bits of an address results in a large-scale circuit. In addition to this, the prior art buffer memory control device must be provided with the overflow occurrence notification circuit which comprises two decoders, the flag resister, and the AND circuit as shown in FIG. 10(b), and detects overflow when the subtraction result changes from "-1" into "0", or the empty occurrence notification circuit which comprises two decoders, the flag register, and the AND circuit as shown in FIG. 10(b), and detects empty when the subtraction changes "+1" into "0".
Further, in order to notify a transfer source that transfer of write data is aborted after overflow has occurred in the buffer memory, it is required that write data before aborting transfer be retransmitted, which beings about loss of the write data before aborting transfer, or loss of data resulting from overwriting onto the buffer memory.
One solution to these problems is to use a cell buffer control circuit, which is disclosed in Japanese Published Patent Application No. Hei- 8-223168, and which has been developed. FIG. 11 shows a construction of this cell buffer memory control circuit. Referring to FIG. 11, the cell buffer memory control circuit comprises a decoder 105 for decoding a write bank address 101, a decoder 106 for decoding a read bank address 103, information holding means 1091.about.109n for holding information indicating whether cell data is present in respective banks, an addition circuit 112 for adding "1" to a value of the write bank address 101, a selector 114 for selecting one of outputs 1101.about.110n from the information holding means 1091.about.109n on the basis of the value of the addition circuit 112, an addition circuit 113 for adding "1" to a value of the read bank address 103, a selector 115 for selecting one of outputs 1101.about.110n from the information holding means 1091-109n on the basis of the value of the addition circuit 113, and abnormal condition detecting means 116 for detecting an abnormal condition of the cell buffer.
In this cell buffer control circuit, the whole cell buffer is divided into n banks, and a write address or a read address is intended for each of the n banks. The information holding means 1091-109n is provided in the corresponding banks, respectively. The decoder 105, at the detection of write termination of cell data onto each bank, input "write termination" to the corresponding information holding means by the use of the write bank address 101 and the bank write termination signal 102, thereby setting a flag therein to indicate there is cell data. The decoder 106, at the completion of reading cell data from each bank, releases the flag held in the corresponding information holding means by the use of the read bank address 103 and the read termination signal 104. Thereby, each information holding means shows whether cell data is written to the corresponding bank and is present therein, or cell data is read therefrom and is not present therein.
By using the value resulting from adding "1" to the write bank address 101 as a control signal of the selector 114, the selector 114 selects one of the outputs 1101.about.110n from the information holding means 1091.about.109n. It follows from the fact that the selector 114 does not select information holding means in a bank to which data should be written but one in a next bank. Accordingly, when a signal 117 output from the selector 114 is H, the cell buffer overflows. For this reason, the signal 117 is used as a write inhibit signal for the cell buffer.
Besides, by using the value resulting from adding "1" to the read bank address 103 as a control signal of the selector 115, the selector 115 selects one of the outputs 1101.about.110n from the information holding means 1091.about.109n. It follows from this fact that the selector 115 does not select information holding means in a bank from which data should be read but one in a next bank. Accordingly, when a signal 118 output from the selector 115 is L, the cell buffer is empty. For this reason, a reverse signal of the signal 118 is used as a read inhibit signal for the cell buffer.
However, this prior art cell buffer control circuit has also drawbacks. The circuit checks information of the information holding means in the next bank, thereby controlling overflow and underflow. Hence, as soon as writing to the bank starts, the circuit outputs a detection result indicating that the bank is about to overflow or underflow, which tends to occur because effective use of the capacity of the cell buffer is not realized with fewer banks. For instance, in case of two banks, only half of a whole capacity of the cell buffer is made use of. As a result, controlling data transfer with the use of the detection of overflow or underflow output from the circuit, results in poor efficiency in transfer.
In addition, the circuit copes with banks of a fixed length.